Testing Semiconductor Memories

An Open Notation for Memory Tests

Aad Offerman and Ad J. van de Goor: An Open Notation for Memory Tests (also available in PostScript format)
(presented at the IEEE International Workshop on Memory Technology, Design and Testing, 1997).

Cited by:

• Michael Linder, Alfred Eder, Ulf Schlichtmann, Klaus Oberlander: An Analysis of Industrial SRAM Test Results – A Comprehensive Study on Effectiveness and Classification of March Test Algorithms, IEEE Design and Test 31(3):42-53, June 2014;
• Michael Linder: Test Set Optimization for Industrial SRAM Testing, Dissertation, Fakultät für Elektrotechnik und Informationstechnik, Technischen Universität München, 2012-2013;
• Sonal Sharma, Vishal Moyal: FSM Based BIST Architecture, International Journal of Engineering Sciences & Management, April-June, 2012;
• M. Linder, A. Eder, K. Oberlander, M. Huch: Variations of fault manifestation during Burn-In — A case study on industrial SRAM test results, IEEE 17th International On-Line Testing Symposium (IOLTS), 2011, pages 218-221;
• A. Kokrady, R. Mehrotra, T.J. Powell, S. Ramakrishnan: Reducing design verification cycle time through testbench redundancy, 19th International Conference on VLSI Design, 2006, pages 6. Held jointly with 5th International Conference on Embedded Systems and Design;
• Zaid Al-Ars: DRAM Fault Analysis and Test Generation, Dissertation, Delft University of Technology, June 2005;
• K. Thaller, A. Steininger: A transparent online memory test for simultaneous detection of functional faults and soft errors in memories, IEEE Transactions on Reliability, Volume 52, Issue 4, pages 413-422, December 2003;
• Farbod Karimi, V. Swamy Irrinki, T. Crosby, Fabrizio Lombardi: Parallel testing of multi-port static random access memories, Microelectronics Journal 34(1):3-21, January 2003;
• F. Karimi, F. Lombardi: A scan-BIST environment for testing embedded memories, Proceedings of the Eighth IEEE International On-Line Testing Workshop, 2002, pages 211-217;
• Z. Al-Ars, A.J. van de Goor, J. Braun, D. Richter: A memory specific notation for fault modeling, 10th Asian Test Symposium, 2001, Proceedings pages 43-48;
• Karl Thaller: A Highly-Efficient Transparent Online Memory Test, Proceedings of the 2001 IEEE International Test Conference, p.230, October 30 - November 1, 2001;
• This email address is being protected from spambots. You need JavaScript enabled to view it.: Programmable Embedded Memory BIST Using Embedded Processor;
• This email address is being protected from spambots. You need JavaScript enabled to view it.: Programmable BIST Architecture to find faults based on defect injection;
• US Patent 6496950: Testing content addressable static memories;
• US Patent 6550032: Detecting interport faults in multiport static memories;
• US Patent 6757854: Detecting faults in dual port FIFO memories.

Aad Offerman and Ad J. van de Goor: An Open Notation for Memory Tests (also available in PostScript format)
(Technical Report No.1-68340-44(1997)07, Delft University of Technology)

Cited by:

• US Patent 8829898: Method and apparatus for testing.

This paper contains the description of a language that was intended to be open, and at the same time handle most of the tests used these days. The result may be a little overwhelming.

We have realized that building and building on top of this open notation is not the way to go in the long run, and are thinking about better solutions at the moment. The next step will probably be a language that looks more like a general programming language providing facilities commonly used in memory tests. Furthermore, it is tempting to try to design notations for the specification of faults and for memory architectures at the same time, and make good use of the fact that the three of them are so closely related. However, this only exists in our heads yet, so no paper on this can be provided at the moment.

Towards a Uniform Notation for Memory Tests

Ad J. van de Goor, Aad Offerman, and Ivo Schanstra: Towards a Uniform Notation for Memory Tests (also available in PostScript format)
(presented at the European Design & Test Conference and Exhibition 96)

Cited by:

• Ireneusz Mrozek, N. A. Shevchenko, Vyacheslav Yarmolik: Universal Address Sequence Generator for Memory Built-in Self-test, DOI:10.48550/arXiv.2208.05325, July 2022;
• B V S Sai Praneeth: Finite State Machine based Programmable Memory Built-in Self-Test, DOI:10.22214/ijraset.2021.35875, June 2021;
• Sonal Sharma, Vishal Moya: Area Optimized FSM Based BIST, International Journal of Engineering Sciences & Management, April-June, 2012, ISSN 2277-5528;
• WonGi Hong, JungDai Choi, Hoon Chang: A programmable memory BIST for embedded memory, International SoC Design Conference, 2008, ISOCC '08, Volume: 02, DOI:10.1109/SOCDC.2008.4815717, December 2008;
• Alexander Ivaniuk, Vyacheslav Yarmolik: A new approach to the design of built-in internal memory self-testing devices, Automatic Control and Computer Sciences 42(4):169-174, DOI:10.3103/S0146411608040019, August 2008;
• Alexander Ivaniuk, A. V. Stepanov: Injection of functional faults into VHDL descriptions of random-access memory devices, Automatic Control and Computer Sciences 42(3):145-152, June 2008;
• Alexander A. Ivaniuk: Optimal Memory Tests Coding for Programmable BIST Architecture, R&I, 2008, No 4;
• Po-Chang Tsai, Sying-Jyan Wang, Feng-Ming Chang: FSM-based programmable memory BIST with macro command, DOI:10.1109/MTDT.2005.24, September 2005;
• Chauchin Su, Shih-Ching Hsiao, Hau-Zen Zhau, Chung-Len Lee: A computer aided engineering system for memory BIST, Proceedings of the 2001 conference on Asia South Pacific design automation, p.492-495, January 2001, Yokohama, Japan;
• A.P. Zankovich, V.N. Yarmolik: Nondestructive RAM Testing by Analyzing the Output Data for Symmetry, Automation and Remote Control, v.64 n.9, p.1488-1500, September 2003;
• Neha Namdev, Rita Jain, Ashutosh Kumar Singh: Low Area FSM based Programmable BIST, International Journal of Computer Technology and Electronics Engineering (IJCTEE), Volume 1, Issue 2, ISSN 2249-6343;
• Shih-Ching Hsiao: Memory Simulator and Tester Control Code Generator, Master's Thesis, Department of Electrical Engineering, National Central University (NSU), Taiwan.

In here you can find a predecessor to the language above that is much more limited (more like an extension to the March test notation) and thus much more cleaner.
For this language a lex & yacc front-end is available.

Thesis Project: Automatic Memory Test Verification and Generation

Abstract

Designing memory tests which are complete and irredundant is hard to do. It is difficult to verify whether a certain test indeed covers all faults it is designed for (verification for completeness), and if it contains elements that can be left out without affecting its completeness (verification for irredundancy).

Therefore, a method is presented to automatically verify the completeness and irredundancy of memory tests. This method includes the definition of a two-dimensional memory model that determines the abstraction level, and the specification of memory characteristics, memory faults, and memory tests.

In the fault specification, a great variety of memory cell array faults and port faults can be specified. There is a strict separation between the behaviour of the fault, and the layout in the memory. Furthermore, the use of natural defaults allows the user to work only at an abstraction level as deep as needed.

To specify memory tests, a new memory test language has been designed. The widely used standard march test language is a natural subset of this memory test language. Furthermore, the memory test language has a much wider applicability than only this specific application; it can be practized for others too.

The presented method has been implemented in the programming language C++ for the UNIX platform and the X Window System grafical user interface. Several interpreters for the memory test language were implemented using the standard UNIX tools lex and yacc.

The complete thesis report (237 pages, in PostScript format).